Analyzing Reverse Address Translation Overheads in Multi-GPU Scale-Up Pods

This collection of systems papers (arXiv, 06 Apr 2026) focuses on performance and scalability optimizations for large-scale ML, simulation, and distributed systems. Key results include: (1) a first systematic study of destination-side Reverse Address Translation in multi-GPU scale-up pods showing cold Link TLB misses can cause up to 1.4x latency degradation and proposing fused pre-translation kernels and software-guided TLB prefetching; (2) heterogeneous memory management techniques that use host memory to overcome GPU memory limits for large-scale nonlinear time-history simulations and to生成s