Graph-ESBMC-PLC: Formal Verification of Graphical PLCopen XML Ladder Diagram Programs Using SMT-Based Model Checking
2026-06-18T08:52:06Z•24a62911c5370dd7c9d629bf33d1af0d85504744ab4478e7da9dd3f8e399094f
BeremizCONTROLLINOEEG classification','machine learningESBMC-PLCGraph-ESBMC-PLCIBM QuantumICSIEC 61131-3Ladder DiagramOpenPLC EditorPLCPLCopen XMLQDSVQIntentQrubaSCADASMT-based model checkingZenodo artifactexecution tracesformal verificationmulti-backend frameworkquantum computingquantum simulatorsemantic representationstatic analysis
What happened
Two arXiv papers: (1) Graph-ESBMC-PLC describes a fix and extension to ESBMC-PLC that correctly parses PLCopen XML graphical Ladder Diagram (LD) exports (CONTROLLINO, Beremiz, OpenPLC Editor) into a full GOTO IR using a DFS-based graph resolver and I/O inference, closing a gap that previously produced an empty IR and vacuous verification results. The work preserves textual LD handling, orders coil semantics to match IEC scan-cycle behavior, and provides validation artifacts. This is relevant to ICS/PLC safety because vacuous verification can give a false sense of security for control logic. (2
Why it matters
A reviewed impact interpretation has not been published for this record.
Evidence and limitations
- Source ID
- arxiv_cs_pl
- Record identifier
- 24a62911c5370dd7c9d629bf33d1af0d85504744ab4478e7da9dd3f8e399094f
- Enrichment time
- 2026-06-18T08:52:06Z
- AI-assisted enrichment
- Yes
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