VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation

This collection contains four CS/PL papers: (1) VHDLSuite introduces an end-to-end pipeline that converts Verilog designs and testbenches into validated, executable VHDL benchmarks (VHDLBench, ~200 tasks) and uses VUnit/GHDL for compilation/test validation to evaluate LLM-driven VHDL code generation. It exposes challenges for LLM-assisted HDL generation and provides an open benchmark and tooling. (2) A theoretical paper on focalisation using relative monads/comonads for modelling resource/effect modalities in call-by-push-value settings; mainly formal PL/semantics contributions. (3) An equa​t​