ESBMC-PLC+: A Unified IEC~61131-3 Formal Verification Framework as a PLCverif Successor

This collection of papers focuses on advances in formal verification, program analysis, and system modeling relevant to safety and assurance. Key contributions: ESBMC-PLC+ (and ESBMC-GraphPLC) unify IEC 61131-3 support (Ladder Diagram, graphical LD, Structured Text) into an ESBMC backend with k-induction/unbounded proofs and explicit timer/counter/trigger semantics for PLCs, closing gaps in PLCverif and improving verification coverage and performance; DissProve introduces a goal-directed, backward unreachability technique to automatically verify safety of asynchronous parametric distributed ("