Type Safety via Hoare Logic with Separation and Pure Types
2026-07-29T08:51:55Z•a033fc989ab0c0af2cf536ff60124ac71a0cd13e315251192d70ef59051f3f7c
Hoare-logicLLM-generated-VerilogPyTorchTorchDynamocompiler-bugsdeep-learning-compilersformal-methodshardware-securitymemory-safetyprobabilistic-analysisprogram-synthesisresearchsoftware-verificationtype-safety
What happened
This document is an arXiv computer science feed containing six research papers on type-safety verification, probabilistic cost analysis, relational program synthesis, deep-learning compiler frontend bugs, LLM-based Verilog specification repair, and reflective arithmetic. One paper reports 23 previously unknown TorchDynamo frontend bugs, 15 of which were confirmed, but the feed does not describe exploitable vulnerabilities or provide vulnerability identifiers.
Why it matters
A reviewed impact interpretation has not been published for this record.
Evidence and limitations
- Source ID
- arxiv_cs_pl
- Record identifier
- a033fc989ab0c0af2cf536ff60124ac71a0cd13e315251192d70ef59051f3f7c
- Enrichment time
- 2026-07-29T08:51:55Z
- AI-assisted enrichment
- Yes
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