Automated Deployment of Real-Time Tasks for Phased Execution on Scratchpad-Based Multicore Platforms

The work proposes a model-based deployment methodology that automates application adaptation for phased execution.

Source: [1], [4]

Its integrated tooling derives task and runtime artifacts and provides runtime orchestration for the target platform.

Source: [1], [4]

The research question concerns automating adaptation and deployment of real-time applications for phased execution on scratchpad-based multicore systems while reducing integration effort.

Source: [1]

The methodology is organized around hardware, task-execution, and schedule aspects in a common system model.

Source: [2], [9]

The schedule model derives a static hyperperiod schedule from periodic task schedules and developer-provided annotations.

Source: [7]

Deployment builds task binaries separately for the cores on which tasks execute and extracts transferable section information from those binaries.

Source: [16]

The process generates a runtime configuration and schedule, builds the runtime artifact, and creates minimal kernels for application cores.

Source: [20]

The tool evaluates schedule feasibility through offset, computation nonoverlap, event-delay, and positive-slack constraints.

Source: [12], [17], [18]

The developer remains responsible for providing a schedule that satisfies the feasibility constraints.

Source: [15]

The assumed platform combines per-core scratchpads, shared main memory, and a management core for execution orchestration.

Source: [3], [10]

The approach requires scratchpads and memory protection; it uses direct memory access where available, while management-core transfers are a lower-performance fallback.

Source: [10]

The implementation study deploys an avionics-control application on a custom FPGA-hosted RISC-V multicore platform with scratchpads, shared memory, an interconnect, and a memory-transfer peripheral.

Source: [22]

Task execution times were measured on the hardware platform rather than established through a worst-case execution-time analysis.

Source: [8], [13]

Memory-transfer behavior was characterized by repeated measurements across a range of transfer sizes and represented with a conservative linear timing model.

Source: [13], [21]

The study reports maximum observed static overheads for schedule events and the task communication and transfer operations, excluding memory-transfer time, based on repeated measurements.

Source: [13], [14]

The methodology was demonstrated through deployment of the case-study application, including a generated schedule and an execution trace covering a hyperperiod; the displayed trace uses an adjusted hyperperiod for visibility.

Source: [5], [19]

Separating runtime and task binaries avoids source-level framework integration and is intended to minimize impact on task implementations.

Source: [16]

The current deployment process requires task implementations to be supplied as C source code.

Source: [16]

Evaluation is confined to the stated case study and its custom FPGA-based RISC-V target platform.

Source: [5], [22]

Support for environment ports that interact with external sensors and actors is identified as future work.

Source: [5]